1. Field of the Invention
The invention relates to a semiconductor device and a method for fabricating the same, and more particularly to a MOS transistor including gate insulators having different thicknesses and a method for fabricating the same.
2. Description of the Related Art
In response to the requirement of higher integration and higher operation speed of a semiconductor device, fabrication technologies have been developed for fabricating a semiconductor element in more minute size and in higher density. It is also required for a semiconductor device to consume lower electrical power and to operate with a lower voltage. These are for responding to scaling down dimension and portability of an apparatus into which a semiconductor device is to be incorporated, and also for preventing malfunction of a semiconductor device to be caused due to increased heat derived from a semiconductor element which is accompanied with higher integration and higher operation speed of a semiconductor device.
If a voltage for operating a semiconductor element is reduced in order to lower electrical power consumption and a voltage at which a semiconductor device is operated, an operation speed of the semiconductor element and hence an operation speed of a semiconductor device including the semiconductor element is also reduced. One of approaches for satisfying the above mentioned requirements contrary to each other is to use two or more operational voltages in a semiconductor device.
A plurality of operational voltages are used also for adequately working a part of circuits constituting a semiconductor device. In such a structure, a semiconductor device is provided with a circuit for increasing a voltage or a circuit for decreasing a voltage in order to generate a desired voltage different from a supply voltage to be supplied to a semiconductor device. The use of a plurality of voltages for operating a semiconductor device makes it possible to apply a plurality of voltages to a gate insulator of a MOS transistor.
With fabrication of a semiconductor element in more minute size, a gate insulator is made thinner. However, if a thickness of gate insulators is uniformly reduced, such gate insulators cannot be used for the above mentioned plurality of voltages for operating a semiconductor device. Namely, if the highest voltage among the plurality of operation voltages is applied, insulating properties of a thinner formed gate insulator is deteriorated. Thus, it is necessary for a gate insulator of a MOS transistor to which a higher voltage is to be applied to have a greater thickness, and for a gate insulator of a MOS transistor to which a lower voltage is to be applied to have a smaller thickness.
For this reason, methods have been developed for forming gate insulators having different thicknesses in a semiconductor device. For instance, Japanese Unexamined Patent Public Disclosure No. 5-291573 laid open on Nov. 5, 1993 has suggested one of such methods.
Hereinbelow will be explained the method, suggested in No. 5-291573, for fabricating a MOS transistor including gate insulators having different thicknesses with reference to FIGS. 1A to 1D which are cross-sectional views of a MOS transistor and arranged in an order with which fabrication steps are carried out.
First, as illustrated in FIG. 1A, a plurality of insulator films 102 for isolating elements from each other are selectively formed on a p-type semiconductor substrate 101 by LOCOS. Then, the insulative films 102 are selectively etched for removal to thereby form recesses 103 (only one of them is illustrated in FIGS. 1A to 1D) at a location where the removed insulative films 102 used to exist.
Then, a gate insulator having a thickness of about 18 nm is deposited by thermal oxidation on exposed surface of the p-type semiconductor substrate 101. Then, as illustrated in FIG. 1B, a resist layer 104 is patterned by means of photolithography over an area B which includes a recess 103 and in which a MOS transistor having a high breakdown voltage of gate oxide is to be fabricated. Then, a gate insulator disposed in an area A is etched for removal with the patterned resist layer 104 serving as a mask- In the area A, a MOS transistor having an normal breakdown voltage is to be fabricated. Thus, a first gate insulator 105 is formed in the area B in which a MOS transistor having a high breakdown voltage of gate oxide is to be fabricated.
After the patterned resist layer 104 has been removed, a resultant is subject to thermal oxidation again to thereby form a second gate insulator 106 having a thickness of about 18 nm in the area A. As illustrated in FIG. 1C, since in the area B has been already formed the first gate insulator 105, the thermal oxidation makes an additional insulator over the first gate insulator 105 with the result that a first insulator 105a having a thickness of about 25 nm is newly formed in the area B.
Then, as illustrated in FIG. 1D, a gate electrode 107, a source diffusion layer 109, and a drain diffusion layer 110 are formed in a conventional manner for a MOS transistor having a high breakdown voltage of a gate insulator. In the same way, a gate electrode 108, a source diffusion layer 111, and a drain diffusion layer 112 are formed in the area A in a conventional manner for a MOS transistor having a normal breakdown voltage.
As having been explained, in the prior method, in order to form the gate insulators 105a and 106 having different thicknesses, the first gate insulator 105 is first deposited, then the first gate insulator 105 is selectively removed in predetermined areas, and then the second gate insulator 106 is deposited all over a resultant.
The above mentioned prior method needs two steps for thermally oxidizing a semiconductor substrate, a step of photolithography, and a step for etching a gate insulator in order to form gate insulators having different thicknesses.
In addition, the above mentioned prior method needs a step for patterning a resist layer between first and second thermal oxidations in formation of a gate insulator of a MOS transistor to which a relatively high voltage is to be applied. For this reason, contamination of a gate insulator with impurities such as heavy metal is not avoidable, and hence quality and/or reliability of a gate insulator is deteriorated. Since the resist layer 104 is in direct contact with the gate insulator 105 in the above mentioned method, heavy metal contained in the resist layer is prone to containinate the gate insulator 105. Thus, it is necessary to provide countermeasure for avoiding such contamination.